The present invention generally relates to field effect transistors (FETs). More particularly, this invention relates to very small dimensioned metal-oxide semiconductor (MOS) FETs in the size range of micrometers (one micrometer or micron, xcexcm, is 10xe2x88x926 meters) to nanometers (one nanometer, nm, is 10xe2x88x929 meters). Fabricated to allow for a higher density of devices on a semiconductor wafer, small MOSFETs may experience certain deleterious performance due to their size. One such problem is short channel effects caused by the limited separation of the source and drain. The inventive fin device and process of making the device alleviate short channel effects associated with MOSFETs having dimensions of micrometers or less.
Since 1960 when integrated circuits (xe2x80x9cICsxe2x80x9d) were first created and fabricated, the number and density of the devices being formed on IC substrates has increased tremendously. Indeed, the very large scale integration (xe2x80x9cVLSIxe2x80x9d) devices, having more than 100,000 devices on a chip, are generally considered old technology. The fabrication of ICs having hundreds of millions of devices on a chip is standard in the market today. The development of ICs with billions of devices on each chip is under current development. Therefore, the current description of IC fabrication is ultra large scale integration (xe2x80x9cULSIxe2x80x9d).
As part of the increase in the number of devices formed on an IC substrate and the concurrent increase in density of the devices, the dimensions of the devices have dropped significantly. In particular, the dimensions of gate thicknesses and channel separation of source and drain elements has continually reduced such that today, micrometer and nanometer separations of the source, drain, and gate are required. Although devices have been steadily reducing in size, the performance of the devices must be maintained or improved. In addition to performance characteristics, performance reliability, and durability of the device, the manufacturing reliability and cost are always critical issues.
Several associated problems arise with the miniaturization of devices, including short channel effects, punch-through, and leakage current. These problems affect both the performance of the device and the manufacturing process. Short channel effects are often observed when the width of the FET channel is less than 0.5 to 1.0 xcexcm. The impact of short channel effects on device performance is seen in the reduction in the device threshold voltage and the increase of sub-threshold current.
More particularly, as the channel length becomes smaller, the source and drain depletion regions may expand towards each other. The depletion regions may essentially occupy the entire channel area between the source and drain. As a result of this effective occupation of the channel area by the source and drain, the channel is in part depleted and the gate charge necessary to alter the source and drain current flow is reduced.
One method for reducing or eliminating short channel effects is to reduce the thickness of the gate oxides adjacent to the source and drain. Not only will thin gate oxides reduce short channel effects, but they also allow for higher drive currents. One result is faster devices. As can be expected, however, there are significant problems associated with fabricating thin oxides, including manufacturing reproducibility and the uniformity and control of the oxide growth rate during the fabrication process.
Attempts to resolve the short channel effects and other problems associated with ULSI devices have been made and are continuing. One such attempt, described by Hisamoto et al. in xe2x80x9cA Folded-Channel MOSFET for Deep-Sub-Tenth Micron Era,xe2x80x9d page 1032, Technical Digest of the 1998 International Electron Devices Meeting, teaches a quasi-planar vertical double-gate MOSFET having a gate length down to 20 nm. The features noted by Hisamoto et al. include a vertical ultra-thin silicon fin; two gates self-aligned with the source and drain; a raised source and drain to reduce parasitic resistance; and a quasi-planar structure. The Hisamoto et al. device appears to be limited to a channel of 20 nm, however, and does not appear to be suited for use in a planarized configuration. Moreover, the fabrication process shown by Hisamoto et al. does not appear to use conventional lithography and spacer techniques.
Another device, disclosed in U.S. Pat. No. 5,675,164 issued to Brunner et al. and assigned to the same applicant as this application, describes a high-performance multi-mesa FET. The FET includes mesa structures in a conduction region, favoring corner conduction, together with lightly doped mesa structures and mid-gap gate material also favoring operation in a fully depleted mode. Although teaching a high performance FET, the Brunner et al. disclosure specifically notes that silicon on insulator (xe2x80x9cSOIxe2x80x9d) structures have certain disadvantages making their use impractical for the multi-mesa FETs.
The metal-insulator-semiconductor (xe2x80x9cMISxe2x80x9d) transistor described in U.S. Pat. No. 4,996,574 issued to Shirasaki for a MIS transistor structure for increasing conductance between source and drain regions has as a primary object to substantially increase the conductance between the source and drain regions while also decreasing the size of the device. As provided in Shirasaki, conventional MOSFET devices using a SOI structure are limited from increasing total current flow (e.g., performance) by the cross sectional area of the channel. According to Shirasaki, to increase the current flow, the channel area must also be increased thereby increasing the overall dimension of the device.
Finally, the abstract to Japanese Patent No. 5,343,679 issued to Daisuke et al., for a semiconductor device and manufacturing method thereof, shows and describes a MOS transistor device that uses different impurities imbedded into the device substrate from the source and drain impurities to enhance the transistor performance characteristics. Although apparently using a vertical fin configuration, the device shown does not result in a planarized device nor does it appear to use standard lithography or spacer techniques in the fabrication of the device.
Accordingly, there remains a need for MOSFETs, of dimensions in the range of micrometers to nanometers, that are capable of using an SOI structure that may be planarized, and that reduce or eliminate the problems of leakage, punch-through, and short channel effects. In addition, there remains a need for, and it would be desirable to have, a reliable fabrication process using conventional lithography and spacer process techniques to manufacture such an SOI device that may be planarized.
To meet these and other needs and to overcome the shortcomings of the prior art, it is an object of the present invention to provide a fin device that is in the size range of a micron or less. Another object is to provide a device that is not restricted by performance limitations of leakage, punch-through, and short channel effects typically associated with FETs having sub-micron dimensions. Still another object is to provide a process of making the device.
To achieve these and other objects, and in view of its purposes, the present invention provides a process for fabricating a fin device as the body for a FET. The process comprises the steps of forming a vertical semiconductor-on-insulator fin on a substrate with an oxide layer on top of a segment of the fin; depositing a polysilicon layer; forming a source and a drain separated by a polysilicon channel on top of the oxide layer that is on top of the segment of the fin; implanting dopants for workfunction adjustments; depositing a silicide layer over the exposed polysilicon layer; depositing an oxide layer over the fin; and polishing the oxide layer.
In another embodiment of the present invention, the process of fabricating the fin device results in a fully planarized device. In yet another embodiment of the present invention, the process of fabricating the fin device results in a source and drain separation in the range of approximately 10 nm. In still another embodiment of the present invention, the process of fabricating the fin device results in an oxide layer separating the fin from the polysilicon having a width approximately in the range of 1.5 nm.
The present invention also encompasses an improved fin device that is fully planarized. The device comprises a substrate, a vertical fin, a polysilicon deposition layer, an oxide layer on top of a segment of the fin and the exposed substrate, a source and drain formed on top of the oxide layer, a polysilicon gate separating the source and drain, dopant implants for work function adjustments, a silicide layer covering the polysilicon gate, and a top oxide layer forming a planarized top surface of the fin device. In another aspect of the present invention, the improved fin device has a separation between the source and drain in the range of approximately 10 nm. In yet another aspect of the present invention, the improved fin device has an oxide layer separating the fin from the polysilicon having a width approximately in the range of 1.5 nm.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.